Tri State Buffers
Tri State Buffers: Motivation
A buffer is generally to be used to pass input to its output as it is with full signal levels to feed to input to other logic. But when we have multiple bus driving to same input logic there may be chances of bus contentions and burn out the logic circuit. To avoid this scenario we use tri state buffers instead of normal buffers which has third control input called enable or control. The behavior can be understood by below figure. When Enable is 1 the data transferred from A to Q but when it is 0 the output Q is disconnected from input A which is called high impedance state.
We will study few scenarios based on above explanation. Below is wired AND or direct connection where multiple buffers output connected to common bus and if not handled properly there may be chances of bus contentions.
Case 1- All enables are 1 : It means all input data can reach on bus and if one data is 1 and another is 0 then the simulator out put would be X. Because it can not resolve to 0 or 1.
Case 2- All enables are 0 : It means all input data can not reach on bus and the simulator out put would be Z(High impedance state).
Case 3- If this connection is wired AND then the result would be AND of Data-Inputs. For example if 2 Enables are 1 then the output would be (Data-In 1 AND Data-In 2).
A buffer is generally to be used to pass input to its output as it is with full signal levels to feed to input to other logic. But when we have multiple bus driving to same input logic there may be chances of bus contentions and burn out the logic circuit. To avoid this scenario we use tri state buffers instead of normal buffers which has third control input called enable or control. The behavior can be understood by below figure. When Enable is 1 the data transferred from A to Q but when it is 0 the output Q is disconnected from input A which is called high impedance state.
We will study few scenarios based on above explanation. Below is wired AND or direct connection where multiple buffers output connected to common bus and if not handled properly there may be chances of bus contentions.
Case 1- All enables are 1 : It means all input data can reach on bus and if one data is 1 and another is 0 then the simulator out put would be X. Because it can not resolve to 0 or 1.
Case 2- All enables are 0 : It means all input data can not reach on bus and the simulator out put would be Z(High impedance state).
Case 3- If this connection is wired AND then the result would be AND of Data-Inputs. For example if 2 Enables are 1 then the output would be (Data-In 1 AND Data-In 2).
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